Method for avoiding livelock on bus bridge receiving multiple requests

ABSTRACT

A method prevents a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The method includes the first step of in response to at least first and second requests being substantially simultaneously received from at least first and second peripherals, determining if a state of a state machine corresponds to an assigned order of either the first peripheral or the second peripheral. The second step includes if the state does not correspond to the assigned order of the first peripheral or the second peripheral, advancing the state and repeating the first step until the state corresponds to one of the first or second peripherals. The third step includes if the state corresponds to the assigned order of either the first or second peripheral, determining if the selected request targets system memory. The fourth step includes if the selected request targets system memory, requesting the host bus bridge to flush all existing I/O requests and postpone any future I/O requests from a central processing unit. The fifth step includes in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed, unmasking the selected request to the bus bridge, thereby granting access of the secondary bus to the selected peripheral.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention contains subject matter which may be related topatent application Ser. Nos. 606,913, and 606,914, and docket numbersAT9-95-142 and AT9-96-006, filed Feb. 26, 1996.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to incompatibility between a host busbridge and one or more bus bridges and, more particularly, but withoutlimitation, to avoiding a livelock condition between a host bus bridgeand a PCI-to-PCI bus bridge.

2. Background Information and Description of the Related Art

FIG. 1 illustrates a schematic diagram of a conventional architectureincluding CPU 100, which could be, for example, PowerPC or x86 based, ahost bus bridge (e.g., memory controller) 102 connected to CPU 100 via64 bit host bus 134, and system memory 102 (e.g., DRAM) connected tohost bus bridge 102. Thirty two bit primary PCI bus 130 interconnectshost bus bridge 102 to a variety of adapters (e.g., SCSIs 114 and 116),peripherals (not shown) and/or adapter slots 118 and 120.

Primary PCI bus 130 is limited on how many electrical loads it candrive. However, PCI bridges may be connected to primary PCI bus 130 sothat additional loads can be added. Illustratively, PCI-to-PCI bridge(herein PCI bridge) 112 connects adapters 122, 124, and 126 viasecondary PCI bus 132 to primary PCI bus 130, while PCI-to-ISA bridge(herein ISA bridge) 104 connects peripherals, such as floppy disk 110,to primary PCI bus 130.

However, because ISA direct memory access (DMA) cannot be suspended onceinitiated, ISA bridge 104 must guarantee that host bus bridge 102 willnot suspend access to system memory 105 after ISA bridge 104 attempts aDMA. To do so, ISA bridge 104 asserts a PCI sideband signal FLUSHREQ* onconnection 106 which, when asserted, requests that host bus bridge 102flush any PCI bus transactions in progress. In response, host bus bridge102 asserts a PCI sideband signal MRMACK* on connection 108 after it hasflushed any PCI transactions in progress, and, will suspend any furtherrequested PCI transactions while it asserts MEMACK*. In this manner,host bus bridge 102 guarantees ISA bridge 104 that it will not suspendaccess to system memory 105 once ISA bridge 104 begins a DMA.

Unfortunately, no such guarantee can be made from host bus bridge 102 toPCI bridge 112. The PCI-to-PCI Bridge Architecture Specification 1.0 andthe PCI Local Bus Specification 2.0 delineate two requirements that cancause a livelock condition. First, PCI bridge 112 must flush itsinternal write buffer 134 before it can allow transfer of data to/fromsecondary PCI bus 132. Second, host bus bridge 102 must complete inprocess I/Os before allowing PCI bridge 112 to store memory write datainto system memory 105. Hypothetically, a livelock condition may occur,for example, when SCSI adapter 122 generates a memory write transaction(e.g., MEMORY WRITE or MEMORY WRITE AND INVALIDATE) targeting systemmemory 105. In response, PCI bridge 112 completes the transaction withSCSI adapter 122 and its peripheral (not shown) and posts the memorywrite data in internal write buffer 134. However, in this hypothetical,before the posted memory write data can be flushed (i.e., written tosystem memory 105), CPU 100 initiates a PCI non-postable transactionthat targets a device on secondary PCI bus 132 and, therefore, mustcross PCI bridge 112.

Non-postable PCI transactions include, for example, MEMORY READ, MEMORYREAD LINE, MEMORY READ MULTIPLE, I/O READ, I/O WRITE, CONFIGURATIONREAD, and CONFIGURATION WRITE. When this sequence occurs, the conditionstriggering the livelock have been established. The PCI-to-PCI BridgeArchitecture Specification 1.0 requires that PCI bridge 112 terminatethe non-posted access from CPU 100 by signalling retry because theposted memory write data reins in its internal write buffer 134. Thisrequirement preserves the x86 and PowerPC processor architectureordering rules necessary for correct operation of device drivers andhardware. Therefore, the posted memory write data in internal writebuffer 134 must be flushed before PCI bridge 112 will allow thenon-posted transaction to proceed. However, host bus bridge 102 will notallow access to system memory 105 by PCI bridge 112 until the PCItransaction initiated by CPU 100 completes. Host bus bridge 102 willsimply repeat the retry transaction continuously. In response, PCIbridge 112 will terminate the transaction by signalling retry because ithas been unable to flush its internal write buffer 134. This will repeatcontinuously, resulting in a PCI bus livelock condition.

Accordingly, there would be great demand for a technique that allowshost bus bridge 102 and PCI bridge 112 to conform to the requirementsdelineated in the PCI-to-PCI Bridge Architecture Specification 1.0 andthe PCI Local Bus Specification 2.0, while avoiding a livelockcondition. This technique should delay secondary PCI bus 132 devicewrite accesses to system memory 105 until a guarantee can be made thathost bus bridge 102 has flushed any PCI transactions in progress andwill postpone any further PCI transactions until all memory write datahas been stored in system memory 105.

SUMMARY

In accordance with the present invention, a method prevent a livelockcondition from occurring between a host bus bridge and a PCI bridge,where the host bus bridge and PCI bridge conform to the specificationdelineated in the PCI-to-PCI Bridge Architecture Specification 1.0 andPCI Local Bus Specification 2.0. Specifically, the method prevents alivelock condition from occurring between a host bus bridge that mustcomplete all in process I/O requests before allowing access to systemmemory and a PCI bridge that must flush its internal write buffer beforeallowing transfer of data to/from a secondary PCI bus. The methodincludes the first step of in response to at least first and secondrequests being substantially simultaneously received from at least firstand second peripherals, determining if a state of a state machinecorresponds to an assigned order of either the first peripheral or thesecond peripheral. The second step includes if the state does notcorrespond to the assigned order of the first peripheral or the secondperipheral, advancing the state and repeating the first step until thestate corresponds to one of the first or second peripherals. The thirdstep includes if the state corresponds to the assigned order of eitherthe first or second peripheral, determining if the selected requesttargets system memory. The fourth step includes if the selected requesttargets system memory, requesting the host bus bridge to flush allexisting I/O requests and postpone any future I/O requests from acentral processing unit. The fifth step includes in response to anotification from the host bus bridge that all I/O requests have beenflushed and that any future I/O requests from the central processingunit will be postponed, unmasking the selected request to the busbridge, thereby granting access of the secondary bus to the selectedperipheral.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic diagram of a conventional architecturesubject to a livelock condition.

FIG. 2 illustrates a schematic diagram of an architecture having aunique bus negotiator for preventing a livelock condition in accordancewith the present invention.

FIG. 3 illustrates a timing diagram of a hypothetical transaction forthe architecture of FIG. 2.

FIG. 4 illustrates the arbitrator in accordance with the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2 illustrates a schematic diagram of architecture 200 having aunique bus negotiator in accordance with the preferred embodiment.Specifically, architecture 200 includes bus negotiator 240, havingPCI-to-PCI bridge (herein PCI bridge) 206 and arbitrator 204. In thepreferred embodiment, PCI bridge 206 is implemented within arbitrator204 (collectively referred to as bus negotiator 240), althougharbitrator 204 could be implemented separately from PCI bridge 206.

Architecture 200 further includes a number of interconnected components,such as any suitable CPU 234 (in the preferred embodiment, a PowerPC604), any suitable host bus bridge 232 (e.g., memory controller)connected to host bus 226, any suitable bus master device (e.g., SCSIadapter 212), and any suitable system memory 202. As previouslydescribed, PCI bridge 206 and host bus bridge 232 conform to thespecifications delineated in the PCI-to-PCI Bridge ArchitectureSpecification 1.0 and PCI Local Bus Specification 2.0.

Primary PCI bus 228 connects a variety of peripherals, such asPCI-to-ISA bridge 208, SCSI adapter 260, and communications adapter 262,to host bus bridge 232 and PCI bridge 206. However, unlike theconventional architecture described in FIG. 1, ISA bridge 208 asserts arequest signal (i.e., ISA REQ₋ 258, "₋ " indicating active LOW) toarbitrator 204, and does not assert a FLUSHREQ₋ sideband signal to hostbus bridge 232 (described in more detail herein). Secondary PCI bus 230connects a variety of peripherals and adapters, such as SCSI adapters212 and 214 and disks 236, 238, and 239, to PCI bridge 206 andarbitrator 204. Alternatively, other arrangements of peripherals couldbe made and/or additional stages of bridges added without departing fromthe scope and spirit of the preferred embodiment.

FIG. 3 illustrates a timing diagram for use with architecture 200 shownin FIG. 2. Referring to FIGS. 2 and 3, at clock 0, primary and secondaryPCI buses 228 and 230 are initially idle, waiting for a primary,secondary, or another stage (not shown) PCI bus device to assert itsREQ₋ signal. Next, for sake of illustration, at clock 1, a PCI device onsecondary PCI bus 230 (e.g., SCSI adapter 212) asserts REQ₋ 322 until itis granted secondary PCI bus access from PCI bridge 206 to initiate aWRITE, MEMORY WRITE or MEMORY WRITE AND INVALIDATE transaction.Arbitrator 204 temporarily masks off the asserted REQ₋ from PCI bridge206. Alternatively, arbitrator 204 could have received an asserted ISAREQ₋ 258 from ISA bridge 208.

In response to a received REQ₋ 322 or 258, at clock 1, arbitrator 204asserts FLUSHREQ₋ 224 to host bus bridge 232. Arbitrator 204 continuesto assert FLUSHREQ₋ 224 until it detects that data from SCSI adapter 212has been successfully delivered to system memory 202 (described in moredetail herein). When host bus bridge 232 has flushed all PCItransactions, it asserts MEMACK₋ 222, which, in this example, occurs atclock 2. Host bus bridge 232 continues to assert MEMACK₋ 222 whilearbitrator 204 asserts FLUSHREQ₋ 224, thereby postponing any furtherhost bus bridge 232 initiated PCI transactions. Similarly, if ISA bridge208 asserted REQ₋ 258, it requests and receives control of primary PCIbus 228 to perform DMA access to system memory 202.

In response to host bus bridge 232 asserting MEMACK₋ 222, at clock 2,arbitrator 204 forwards the asserted SCSI adapter 212 REQ₋ to PCI bridge206 on G₋ REQ₋ 220, thereby allowing PCI bridge 206 to detect therequest. In response, PCI bridge 206 asserts GNT₋ to the requestingdevice (e.g., SCSI adapter 212) at clock 3, thereby relinquishingcontrol of secondary PCI bus 230 to the requesting device (e.g., SCSIadapter 212). In response, the requesting device will initiate asecondary PCI bus transaction by asserting PCI signal FRAME* at clock 4.If the initiated PCI transaction is a postable PCI transaction targetingsystem memory 202 (e.g., MEMORY WRITE or MEMORY WRITE AND INVALIDATE),the requesting device writes data into internal write buffer 252 of PCIbridge 206. Otherwise, arbitrator 204 de-asserts FLUSHREQ₋ and controlreturns to the idle state of clock 1.

In response to the requesting device de-asserting FRAME* at clock 8,indicating it has finished transmitting data to internal write buffer252, arbitrator 204 asserts DISPST* 218 for two clock cycles at clock 8to determine the status of internal write buffer 252. PCI bridge 206responds within one clock cycle (i.e., clock 9) by asserting BUFNE* 216,indicating that the posted internal write buffer 252 is not empty.Otherwise, PCI bridge 206 fails to assert BUFNE* 216, indicating thatthe posted internal write buffer 252 is empty. In BUFNE* 216 isasserted, at clock A, arbitrator 204 de-asserts DISPST* 218 and waitsfor PCI bridge 206 to de-assert BUFNE* 216, indicating that postedinternal write buffer 252 has been flushed to system memory 202. In thisexample, PCI bridge 206 de-asserts BUNFE* 216 at clock B and, inresponse, arbitrator 204 de-asserts FLUSHREQ₋ 224 at clock B. Inresponse to FLUSHREQ₋ 224 being de-asserted, host bus bridge 232de-asserts MEMACK₋ 222 at clock C.

Accordingly, arbitrator 204 allows host bus bridge 232 and PCI bridge206 to conform to the requirements delineated in the PCI-to-PCI BridgeArchitecture Specification 1.0 and the PCI Level Bus Specification 2.0,while avoiding a livelock condition. To do so, arbitrator 204 delayssecondary PCI bus 230 device write accesses to system memory 202 until aguarantee is made from host bus bridge 232 that it has flushed any PCItransactions in progress and will postpone any further PCI transactionsuntil all memory write data has been stored in system memory 202.

FIG. 4 illustrates a detailed view of arbitrator 204. Arbitrator 204includes two 24 pin logic chips, namely first logic 400 and second logic450. However, one skilled in the art readily recognizes that additionalchips or other hardware configurations could be utilized to perform thedescribed functions. Pin designations and descriptions are providedbelow. An "₋ " after any pin name indicates active LOW:

    __________________________________________________________________________    PIN Declarations For First Logic 400                                          PIN 1                                                                             PCICLK    COMB.                                                                             ; CLOCK INPUT                                               PIN 2                                                                             EISA.sub.-- FLUSHREQ.sub.--                                                             COMB.                                                                             ; INPUT, GENERATED BY ISA BRIDGE                            PIN 3                                                                             SAD31     COMB.                                                                             ; INPUT, HIGH ORDER ADR/DATA BIT ASSERTED BY                                    ANY DEVICE ON SECONDARY BUS 230 INDICATING                                    USE OF MEMORY CONTROLLER;                                 PIN 4                                                                             SCBE0     COMB.                                                                             ; INPUT, SIDEBAND SIGNAL ASSERTED BY ANY DEVICE                                 ON SECONDARY BUS 230 INDICATING A WRITE                   PIN 5                                                                             SFRAME.sub.--                                                                           COMB.                                                                             ; INPUT, ASSERTED BY A DEVICE WHEN IT TAKES                                     CONTROL OF SECONDARY BUS 230                              PIN 6                                                                             SIRDY.sub.--                                                                            COMB.                                                                             ; INPUT, ASSERTED BY A DEVICE ON SECONDARY BUS                                  230 WHEN IT IS READY TO TRANSMIT DATA                     PIN 7                                                                             STRDY.sub.--                                                                            COMB.                                                                             ; INPUT, ASSERTED BY TARGET DEVICE WHEN IT IS                                   READY TO RECEIVE DATA ON SECONDARY BUS 230                                    (E.G., PCI BRIDGE 206)                                    PIN 8                                                                             SERIALREQ.sub.--                                                                        COMB.                                                                             ; INPUT GENERATED BY SECOND LOGIC 450                                           INDICATING A REQUEST IS WAITING FROM DEVICE                                   ON SECONDARY BUS 230                                      PIN 9                                                                             BUFNE.sub.--                                                                            COMB.                                                                             ; INPUT, ASSERTED BY PCI BRIDGE 206 WHEN                                        INTERNAL WRITE BUFFER 252 IS NOT EMPTY                    PIN 10                                                                            MEMACK.sub.--                                                                           COMB.                                                                             ; INPUT GENERATED BY HOST BUS BRIDGE 232                                        INDICATING IT HAS FLUSHED CPU I/O'S AND WILL                                  POSTPONE OTHERS                                           PIN 11                                                                            SCBE2     COMB.                                                                             ; INPUT ASSERTED BY DEVICE ON SECONDARY BUS 230                                 INDICATING READ OR WRITE DEPENDING ON SCBEO               PIN 12                                                                            GND           ; GROUND                                                    PIN 13                                                                            NC            ; NO CONNECTION                                             PIN 14                                                                            CPU.sub.-- FLUSHREQ.sub.--                                                              COMB.                                                                             ; OUTPUT TO HOST BUS BRIDGE 232 REQUESTING IT                                   TO FLUSH ALL I/O'S AND POSTPONE OTHERS                    PIN 15                                                                            DMAW.sub.--                                                                             REG.                                                                              ; OUTPUT, ASSERTED INDICATING MEMORY ACCESS                                     WRITE BY A DEVICE ON SECONDARY BUS 230                    PIN 16                                                                            LCPU.sub.-- FLUSHREQ.sub.--                                                             REG.                                                                              ; OUTPUT, LATCHED FLUSHREQ.sub.--                           PIN 17                                                                            LDISPST.sub.--                                                                          REG.                                                                              ; OUTPUT TO PCI BRIDGE 206 WANTING TO KNOW IF                                   ANY DATA IS IN INTERNAL WRITE BUFFER 252                  PIN 18                                                                            LSFRAME.sub.--                                                                          REG.                                                                              ; OUTPUT, LATCHED FRAME.sub.--                              PIN 19                                                                            LOCKOUT.sub.--                                                                          REG.                                                                              ; OUTPUT TO SECOND LOGIC 450                                PIN 20                                                                            LSERIALREQ.sub.--                                                                       REG.                                                                              ; OUTPUT, LATCHED SERIAL REQ.sub.--                         PIN 21                                                                            DMAR.sub.--                                                                             REG.                                                                              ; OUTPUT, ASSERTED WHEN DEVICE ON SECONDARY BUS                                 DESIRES MEMORY ACCESS READ                                PIN 22                                                                            NEXT.sub.-- STATE.sub.--                                                                REG.                                                                              ; OUTPUT TO SECOND LOGIC 450, ADVANCE TO NEXT                                   STATE IF THERE IS ANOTHER REQ WAITING                     PIN 23                                                                            G.sub.-- MEMACK.sub.--                                                                  REG.                                                                              ; OUTPUT TO SECOND LOGIC 450                                PIN 24                                                                            VCC                                                                       PIN Declarations For Second Logic 450                                         PIN 1                                                                             PCICLK    COMB.                                                                             ; INPUT CLOCK                                               PIN 2                                                                             LOCKOUT.sub.--                                                                          COMB.                                                                             ; INPUT FROM FIRST LOGIC 400                                PIN 3                                                                             NEXT.sub.-- STATE.sub.--                                                                COMB.                                                                             ; INPUT FROM FIRST LOGIC 400                                PIN 4                                                                             G.sub.-- MEMACK.sub.--                                                                  COMB.                                                                             ; INPUT FROM FIRST LOGIC 400                                PIN 5                                                                             REQ0.sub.--                                                                             COMB.                                                                             ; INPUT REQUEST FROM DEVICE O ON SECONDARY BUS                                  230                                                       PIN 6                                                                             REQ1.sub.--                                                                             COMB.                                                                             ; INPUT REQUEST FROM DEVICE 1 ON SECONDARY BUS                                  230                                                       PIN 7                                                                             REQ2.sub.--                                                                             COMB.                                                                             ; INPUT REQUEST FROM DEVICE 2 ON SECONDARY BUS                                  230                                                       PIN 8                                                                             REQ3.sub.--                                                                             COMB.                                                                             ; INPUT REQUEST FROM DEVICE 3 ON SECONDARY BUS                                  230                                                       PIN 9                                                                             REQ4.sub.--                                                                             COMB.                                                                             ; INPUT REQUEST FROM DEVICE 4 ON SECONDARY BUS                                  230                                                       PIN 10                                                                            MEMACK.sub.--                                                                           COMB.                                                                             ; INPUT FROM FIRST LOGIC 400                                PIN 11                                                                            NC            ; NO CONNECTION                                             PIN 12                                                                            GND           ; GROUND                                                    PIN 13                                                                            NC            ; NO CONNECTION                                             PIN 14                                                                            GREQ0.sub.--                                                                            COMB.                                                                             ; OUTPUT TO PCI BRIDGE 206 CORRESPONDING TO                                     REQUEST 0 FROM A DEVICE 0 ON SECONDARY BUS                                    230                                                       PIN 15                                                                            GREQ1.sub.--                                                                            COMB.                                                                             ; OUTPUT TO PCI BRIDGE 206 CORRESPONDING TO                                     REQUEST 1 FROM A DEVICE 1 ON SECONDARY BUS                                    230                                                       PIN 16                                                                            GREQ2.sub.--                                                                            COMB.                                                                             ; OUTPUT TO PCI BRIDGE 206 CORRESPONDING TO                                     REQUEST 2 FROM A DEVICE 2 ON SECONDARY BUS                                    230                                                       PIN 17                                                                            GREQ3.sub.--                                                                            COMB.                                                                             ; OUTPUT TO PCI BRIDGE 206 CORRESPONDING TO                                     REQUEST 3 FROM A DEVICE 3 ON SECONDARY BUS                                    230                                                       PIN 18                                                                            GREQ4.sub.--                                                                            COMB.                                                                             ; OUTPUT TO PCI BRIDGE 206 CORRESPONDING TO                                     REQUEST 4 FROM A DEVICE 4 ON SECONDARY BUS                                    230                                                       PIN 19                                                                            STATE0    REG.                                                                              ; FIRST ORDER BIT OF STATE MACHINE                          PIN 20                                                                            STATE1    REG.                                                                              ; SECOND ORDER BIT OF STATE MACHINE                         PIN 21                                                                            STATE2    REG.                                                                              ; THIRD ORDER BIT OF STATE MACHINE                          PIN 22                                                                            MULTIPLE.sub.-- REQS.sub.--                                                             REG.                                                                              ; OUTPUT TO FIRST LOGIC 400 INDICATING THERE IS                                 MULTIPLE REQUESTS FROM DEVICES ON SECONDARY                                   BUS 230                                                   PIN 23                                                                            SERIALREQ.sub.--                                                                        COMB.                                                                             ; OUTPUT TO FIRST LOGIC 400 INDICATES THERE IS                                  ANOTHER REQ WAITING                                       PIN 24                                                                            VCC                                                                       __________________________________________________________________________

For ease in explanation, detailed logic for first logic 400 is describedbelow. A "*" represents a logical AND, a "+" represents a logical OR, a"/" before a name represents a logical NOT., and a ":" before "="represents "latched" (i.e., state can only change on rising edge ofclock). Again, a "₋ " after a name represents active LOW.

1. Latched FRAME--Indicates FRAME is latched on PCI clock edgetransitioning from HIGH to LOW.

    /LSFRAME.sub.- :=/SFRAME.sub.-

2. As indicated by the logic below, first logic 400 asserts NEXT₋ STATE₋on the first clock of FRAME (i.e., LSFRAME₋ not asserted) to informsecond logic 450 that a secondary PCI bus cycle utilizing memory 202(i.e., DMA R/W, indicated by asserted SFRAME, SAD31 and SCBE2) hasstarted and that the STATE (i.e., determined by three state machine bitsSTATE0, STATE1, and STATE2, described in more detail herein) should nowbe advanced to the next state because there is at least one REQ₋waiting, which will be indicated by SERIALREQ₋ being asserted. NEXT₋STATE₋ de-asserts once it detects that SERIALREQ₋ has de-asserted (i.e.,no more REQs₋ or MULTIPLE₋ REQs₋ asserted), or that PCI bus 230 is idle(i.e., SFRAME and SIRDY de-assert).

    __________________________________________________________________________    /NEXT.sub.-- STATE.sub.-- := (LSFRAME.sub.--  * /SFRAME.sub.--  * SAD31 *     SCBE2 * /SERIALREQ.sub.--) +                                                      (/NEXT.sub.-- STATE.sub.--  * /(SFRAME.sub.--  * SIRDY.sub.--) *          /SERIALREQ.sub.--)                                                            __________________________________________________________________________

3. First logic 400 asserts DMAW₋ on the first clock edge of SFRAME if itdetects a direct memory access (DMA) write operation (i.e., SCBE0,SAD31, and SCBE2 all asserted). DMAW₋ remains asserted as long as a DMAwrite operation is asserted, or until secondary PCI bus 230 is idle.

    __________________________________________________________________________    /DMAW.sub.-- := (LSFRAME.sub.--  * /SFRAME.sub.--  * SCBE0 * SAD31 *          SCBE2) + (/DMAW.sub.--  *                                                         /(SFRAME.sub.--  * SIRDY.sub.--))                                         __________________________________________________________________________

4. First logic 400 asserts DMAR₋ on the first clock edge of SFRAMED₋ ifa DMA read operation is detected. DMAR₋ remains asserted until the firstdata transfer is detected, or PCI bus is idle.

    __________________________________________________________________________    /DMAR.sub.-- := (LSFRAME.sub.--  * /SFRAME.sub.--  * /SCBE0 * SAD31 *         SCBE2) +                                                                          (/DMAR.sub.--  * /(/SIRDY.sub.--  * /STRDY.sub.--) * /(SFRAME.sub.--      * SIRDY.sub.--))                                                              __________________________________________________________________________

5. LDISPST₋ asserts on the first data transfer of a DMA write. When itasserts, PCI bridge 206 will respond by asserting BUFNE₋ if it hasposted data in its internal write buffer 252. Once the assertion ofBUFNE₋ is detected, LDISPST₋ de-asserts.

    /LDISPST.sub.- :=(/DMAW.sub.- */SIRDY.sub.- */STRDY.sub.-)+(/LDISPST.sub.- *BUFNE.sub.-)

6. First logic 400 transmits LOCKOUT₋ to second logic 450 to prevent thedetection of a re-asserted SERIALREQ₋ for the duration of a PCI buscycle and until delivery is made of any posted write data to memory.That is, once SERIALREQ₋ de-asserts, LOCKOUT₋ asserts and will remainasserted until the PCI bus cycle completes and any data in internalwrite buffer 252 flushes. Therefore, if REQ2₋ is asserted while REQ3₋ isbeing processed, the assertion of SERIALREQ₋ will not effect CPU₋FLUSHREQ₋ until LOCKOUT₋ is de-asserted. Also, REQ2₋ will not be gatedto PCI bridge 206 as GREG2₋ until LOCKOUT₋ de-asserts (describedherein).

    __________________________________________________________________________    /LOCKOUT.sub.-- := (SERIALREQ.sub.--  * ((LSFRAME.sub.--  *                   /SFRAME.sub.--) + /DMAW.sub.--  + /DMAR.sub.-- +                                   /LDISPST.sub.--  + /BUFNE.sub.--)) + (/LOCKOUT.sub.--  *                 ((LSFRAME.sub.--  * /SFRAME.sub.--) +                                              /DMAW.sub.--  + /DMAR.sub.--  + /LSIDPST.sub.--  + /BUFNE.sub.--))       __________________________________________________________________________

7. LSERIALREQ₋ is a latched version of SERIALREQ₋.

    /LSERLALREQ.sub.- :=/SERIALREQ.sub.-

8. Logic 400 asserts CPU₋ FLUSHREQ₋ to alert host bus bridge 232 that avalid DMA request to read or write data in memory is desirous, and thathost bus bridge 232 must flush all PCI buffers (not shown) and hold offPCI cycles. CPU₋ FLUSHREQ₋ asserts when SERIALREQ₋ is or was recentlyasserted, and LOCKOUT₋ is not asserted. CPU₋ FLUSHREQ₋ remains assertedduring the assertion of SFRAME for memory R/W, LDISPST, BUFNE, or ISA₋FLUSHREQ₋. Host bridge 232 responds with MEMACK₋.

    __________________________________________________________________________    /CPU.sub.-- FLUSHREQ.sub.--  = ((/SERIALREQ.sub.--  + /LSERIALREQ.sub.--)     * LOCKOUT.sub.--) + ((LSFRAME.sub.--  * /SFRAME.sub.--                              * SAD31 * SCBE2) + /DMAW.sub.--  + /DMAR.sub.--  + /LDISPST.sub.--      + /BUFNE.sub.--  +                                                                   /EISA.sub.-- FLUSHREQ.sub.--)                                          __________________________________________________________________________

9. Latched CPU₋ FLUSHREQ₋.

    /LCPU.sub.- FLUSHREQ.sub.- :=/CPU.sub.- FLUSHREQ.sub.-

10. Logic 400 asserts gated MEMACK₋ to the GREQ₋ logic in logic 450(described herein). G₋ MEMACK will assert if FLUSHREQ₋ was asserted lastclock cycle (i.e., /LCPU₋ FLUSHREQ₋) and FLUSHREQ₋ continues to beasserted (i.e., /CPU₋ FLUSHREQ₋). Once asserted, G₋ MEMACK remainsasserted until CPU₋ FLUSHREQ₋ de-asserts.

    __________________________________________________________________________    /G.sub.-- MEMACK.sub.-- := (/MEMACK.sub.--  * /LCPU.sub.-- FLUSHREQ.sub.--      * /CPU.sub.-- FLUSHREQ.sub.--) + (/G.sub.-- MEMACK.sub.--  *                      /CPU.sub.-- FLUSHREQ.sub.--)                                            __________________________________________________________________________

Detailed logic for second logic 450 is described below.

1. Second logic 450 asserts MULTIPLE₋ REQS₋ when more than one REQ ispending.

    __________________________________________________________________________    /MULTIPLE.sub.-- REQS.sub.-- :=                                                          /((REQ0.sub.--  *                                                                    REQ1.sub.--  *                                                                      REQ2.sub.--  *                                                                      REQ3.sub.--  *                                                                      REQ4.sub.--) +                                        (REQ0.sub.--  *                                                                     REQ1.sub.--  *                                                                      REQ2.sub.--  *                                                                      REQ3.sub.--  *                                                                      REQ4.sub.--) +                                        (REQ0.sub.--  *                                                                    /REQ1.sub.--  *                                                                      REQ2.sub.--  *                                                                      REQ3.sub.--  *                                                                      REQ4.sub.--) +                                        (REQ0.sub.--  *                                                                     REQ1.sub.--  *                                                                     /REQ2.sub.--  *                                                                      REQ3.sub.--  *                                                                      REQ4.sub.--) +                                        (REQ0.sub.--  *                                                                     REQ1.sub.--  *                                                                      REQ2.sub.--  *                                                                     /REQ3.sub.--  *                                                                      REQ4.sub.--) +                                        (REQ0.sub.--  *                                                                     REQ1.sub.--  *                                                                      REQ2.sub.--  *                                                                      REQ3.sub.--  *                                                                     /REQ4.sub.--))                             __________________________________________________________________________

2. Second logic 450 asserts SERIALREQ₋ if the asserted REQn₋ correspondsto the current state, e.g., REQ2 is asserted and STATE=010 (i.e., highorder bit STATE2 is not asserted, middle order bit STATE1 is asserted,and low order bit STATE0 is not asserted). SERIALREQ₋ is de-asserted ifboth MULTIPLE₋ REQS₋ and NEXT₋ STATE₋ are asserted simultaneously (whichforces the STATE to change to the next state), there are no more REQs,or the asserted REQ de-asserts.

    ______________________________________                                        /SERIALREQ.sub.-- =                                                                     (MULTIPLE.sub.-- REQS.sub.--  + NEXT.sub.-- STATE.sub.--) *                ((/REQ0.sub.--  *                                                                     /STATE2 * /STATE1 * /STATE0) +                                         (REQ1.sub.--  *                                                                      /STATE2 * /STATE1 *  STATE0) +                                         (/REQ2.sub.--  *                                                                     /STATE2 *  STATE1 * /STATE0) +                                         (/REQ3.sub.--  *                                                                     /STATE2 *  STATE1 *  STATE0) +                                         (/REQ4.sub.--  *                                                                      STATE2 * /STATE1 * /STATE0))                                  ______________________________________                                    

3. Second logic generates STATE MACHINE terms to define the statetransitions. The state transitions occur if SERIALREQ₋ is not asserted,and another REQn is pending or more than one REQn are pending. States 0,1, 2, 3, & 4 directly correspond to the input reqs REQ0₋, REQ1₋, REQ2₋,REQ3₋, a REQ4₋.

    __________________________________________________________________________    STATE2 := ((/SERIALREQ.sub.--  * STATE2) + (SERIALREQ.sub.--  *                       ((/STATE2 * STATE1 * STATE0 * /REQ4.sub.--) +                                 (/STATE2 * STATE1 * /STATE0 * /REQ4.sub.--  * REQ3.sub.--) +                  (/STATE2 * /STATE1 * STATE0 * /REQ4.sub.--  * REQ3.sub.--  *                  REQ2.sub.--) +                                                                (/STATE2 * /STATE1 * /STATE0 * /REQ4.sub.--  * REQ3.sub.--  *                 REQ2.sub.--  * REQ1.sub.--) +                                                 (STATE2 * /STATE1 * /STATE0 * /REQ4.sub.--  *REQ3.sub.--  *                   REQ2.sub.--  * REQ1.sub.--                                                    REQ0.sub.--) +                                                                (STATE2 * REQ3.sub.--  * REQ2.sub.--  * REQ1.sub.--  *                        REQ0.sub.--  ))))                                                     STATE1 := ((/SERIALREQ.sub.--  * STATE1) + (SERIALREQ.sub.--  *                       ((/STATE2 * /STATE1 * STATE0 * /REQ2.sub.--) +                                (/STATE2 * /STATE1 * /STATE0 * /REQ2.sub.--  * REQ1.sub.--) +                 (STATE2 * /STATE1 * /STATE0 * /REQ2.sub.--  * REQ1.sub.--  *                  REQ0.sub.--) +                                                                (/STATE2 * STATE1 * STATE0 * /REQ2.sub.--  * REQ1.sub.--  *                   REQ0.sub.--  * REQ4.sub.--) +                                                 (/STATE2 * STATE1 * /STATE0 * /REQ3.sub.--) +                                 (/STATE2 * /STATE1 * STATE0 * /REQ3.sub.--  * REQ2.sub.--) +                  (/STATE2 * /STATE1 * /STATE0 * /REQ3.sub.--  * REQ2.sub.--  *                 REQ1.sub.--) +                                                                (STATE2 * /STATE1 * /STATE0 * /REQ3.sub.--  * REQ2.sub.--  *                  REQ1.sub.--  * REQ0.sub.--) +                                                 (STATE1 * REQ4.sub.--  * REQ1.sub.--  * REQ0.sub.--))))               STATE0 := ((/SERIALREQ.sub.--  * STATE0) + (SERIALREQ.sub.--  *                       ((/STATE2 * /STATE1 * /STATE0 * /REQ1.sub.--) +                               (STATE2 * /STATE1 * /STATE0 * /REQ1.sub.--  * REQ0.sub.--) +                  (/STATE2 * STATE1 * STATE0 * /REQ1.sub.--  * REQ0.sub.--  *                   REQ4.sub.--  ) +                                                              (/STATE2 * STATE1 * /STATE0 * /REQ1.sub.--  * REQ0.sub.--  *                  REQ4.sub.--  REQ3.sub.--) +                                                   (/STATE2 * STATE1 * /STATE0 * /REQ3.sub.--) +                                 (/STATE2 * /STATE1 * STATE0 * /REQ3.sub.--  * REQ2.sub.--) +                  (/STATE2 * /STATE1 * /STATE0 * /REQ3.sub.--  * REQ2.sub.--  *                 REQ1.sub.--) +                                                                (STATE2 * /STATE1 * /STATE0 * /REQ3.sub.--  * REQ2.sub.--  *                  REQ1.sub.--  * REQ0.sub.--) +                                                 (STATE0 * REQ4.sub.--  * REQ2.sub.--  * REQ0.sub.--))))               __________________________________________________________________________

4. GREQn₋ is used to present only one REQn₋ at a time to PCI bridge 206.REQn₋ will only be forwarded to GREQn₋ if: REQn₋ is asserted, STATEn₋ isin the corresponding state (e.g. REQ1₋ & STATE=001), G₋ MEMACK₋ isasserted indicating that logic 400 is ready, LOCKOUT₋ is de-assertedindicating logic 400 is not busy, and MULTIPLE₋ REQS₋ and NEXT₋ STATE₋are not both asserted (indicating that SERIALREQ₋ has not been forcedinactive so that the STATE can advance to next state).

    __________________________________________________________________________    /GREQ0.sub.--  = /REQ0.sub.--  * /STATE2 * /STATE1 * /STATE0 *                /G.sub.-- MEMACK.sub.--  * LOCKOUT.sub.--  * (MULTIPLE.sub.-- REQS.sub.--      + NEXT.sub.-- STATE.sub.--)                                                  /GREQ1.sub.--  = /REQ1.sub.--  * /STATE2 * /STATE1 * STATE0 *                 /G.sub.-- MEMACK.sub.--  * LOCKOUT.sub.--  * (MULTIPLE.sub.-- REQS.sub.--      + NEXT.sub.-- STATE.sub.--)                                                  /GREQ2.sub.--  = /REQ2.sub.--  * /STATE2 * STATE1 * /STATE0 *                 /G.sub.-- MEMACK.sub.--  * LOCKOUT.sub.--  * (MULTIPLE.sub.-- REQS.sub.--      + NEXT.sub.-- STATE.sub.--)                                                  /GREQ3.sub.--  = /REQ3.sub.--  * /STATE2 * STATE1 * STATE0 *                  /G.sub.-- MEMACK.sub.--  * LOCKOUT.sub.--  * (MULTIPLE.sub.-- REQS.sub.--      + NEXT.sub.-- STATE.sub.--)                                                  /GREQ4.sub.--  = /REQ4.sub.--  * STATE2 * /STATE1 * /STATE0 *                 /G.sub.-- MEMACK.sub.--  * LOCKOUT.sub.--  * (MULTIPLE.sub.-- REQS.sub.--      + NEXT.sub.-- STATE.sub.--)                                                  __________________________________________________________________________

While the invention has been shown and described with reference toparticular embodiments thereof, it will be understood by those skilledin the art that the foregoing and other changes in form and detail my bemade therein without departing from the spirit and scope of theinvention.

I claim:
 1. A computer-implemented method for preventing a livelockcondition between a host bus bridge and a bus bridge, the bus bridgehaving an internal write buffer, wherein the host bus bridge mustcomplete all I/O requests for a central processing unit before allowingthe bus bridge access to a system memory, and the bus bridge must flushthe internal write buffer before permitting the host bus bridge toaccess a plurality of peripherals on a secondary bus, comprising thesteps of:(a) in response to at least first and second requests beingsubstantially simultaneously received from at least first and secondperipherals, determining if a state of a state machine corresponds to anassigned order of either the first peripheral or the second peripheral;(b) if the state does not correspond to the assigned order of the firstperipheral or the second peripheral, advancing the state and repeatingstep (a) until the state corresponds to one of the first or secondperipherals; (c) if the state corresponds to the assigned order ofeither the first or second peripheral, determining if the selectedrequest targets the system memory; (d) if the selected request targetsthe system memory, requesting the host bus bridge to flush all existingI/O requests and postpone any future I/O requests from the centralprocessing unit; and (e) in response to a notification from the host busbridge that all I/O requests have been flushed and that any future I/Orequests from the central processing unit will be postponed, unmaskingthe selected request to the bus bridge, thereby granting access of thesecondary bus to the selected peripheral.
 2. The method according toclaim 1, further comprising the steps of:(f) in response to the selectedperipheral accessing the secondary bus and targeting the system memory,advancing the state of the state machine; (g) in response to theselected peripheral accessing the secondary bus, preventing the host busbridge from flushing all existing I/O requests and postponing any futureI/O requests from the central processing unit in response to the activenon-selected request; and (h) in response to the selected peripheralreleasing access to the secondary bus, repeating steps (b) through (g)using the non-selected request.